Chu-Hsin (Jewel) Liang, was born in Taipei Taiwan in 1977. She received her B.S. degree in Electronics Engineering and Computer and Information Science from National Chaio Tung University in 1999. She received the M.S. degree in Electronics from National Chiao Tung University in 2001 and the 2nd from California Institute of Technology in 2004.
She was a senior engineer in Infineon Technology North America in Hopewell Junction New York 2004-2011, where she worked on FEOL device modeling and BEOL parasitic extraction from CMOS 65 to 20nm deep sub-micron technologies. She was a lead engineer in Common Platform Alliance device modeling group. She is currently a senior engineer in Intel Santa Clara California, where she is working on advanced device modeling and CMOS component design for Intel advanced non-volatile memory solution.