Click Here for Free Open Access Full Paper pdf from IEEE

A 2 × 2 D-band active radiator tile is designed in 22-nm CMOS fully depleted silicon on insulator (FDSOI). The tile uses commercial materials, fabrication, and assembly techniques while relaxing printed circuit board (PCB) requirements by eliminating D-band routing. This is accomplished by fully integrating the D-band signal generation, amplification, phase shifting, and antenna coupling structures onto the chip. The phase shifting is accomplished without requiring I/Q generation using the on-chip frequency multipliers. The on-chip power amplifiers (PAs) directly excite off-chip patch antennas via aperture coupling from the chip to the PCB, avoiding the need for costly transitions off-chip. The tile is aligned and assembled with the antenna using flip-chip bonding, which also provides all the low-frequency interconnects for the chip A 2 × 4 array using two of the tiles, demonstrating the scalability of the system, achieves a narrow inter-chip element spacing of 0.6 λ at 140 GHz, a peak effective isotropic radiated power (EIRP) of + 23.5 dBm, and a scan range of ± 40 ∘ while dissipating 77 mW per element.