An Active Analog Delay and the Delay Reference Loop

J. Buckwalter and A. Hajimiri

Wireline signal processing circuits such as transversal equalizers rely on true time delay. An active analog delay stage is proposed that requires a sixteenth of the area of a comparable LC delay line. A delay reference loop is also presented to tune the delay stage against process, voltage, and temperature variations. A reference signal is introduced to tune the delay. The impact of non-idealities must be considered to understand the relationship between the reference frequency and the locked time delay. A SiGe BiCMOS implementation of the active analog delay stage and delay reference loop is presented that operates to 10Gb/s.