Instantaneous Clockless Data Recovery and Demultiplexing

B. Analui, A. Hajimiri

An alternative architecture for instantaneous data recovery for burst-mode communication is introduced. The architecture can perform 1: demultiplexing without additional clock recovery phase-locked loop or sampling blocks. A finite-state machine (FSM) is formed with combinational logic and analog LC transmission line delay cells in a feedback loop. The FSM responds to input data transitions instantaneously and sets the outputs. The system reduces unit interval jitter by a factor of . The new architecture is demonstrated via a SiGe 1:2 clockless demultiplexer circuit that operates at 7.5 Gb/s.